Sean Lie on Why 3D DRAM Packaging Beats Silicon Logic
Cerebras CTO Sean Lie explains why AI chip scaling now depends on 3D DRAM stacking, power delivery, and cooling rather than logic design.
The Inference Frontier: from 100 to 10,000 tokens per second — Sean Lie, Cerebras CTO
With swyx, Sean Lie · Sunday, September 6, 2026
Cerebras co-founder and CTO Sean Lie joins swyx following Hot Chips to discuss the launch of the CS-4 wafer-scale system, preview the roadmap to 10,000 tokens per second on CS-5, and analyze OpenAI's new Jalapeño chip. Lie breaks down why 100–200 TPS is becoming the new batch mode, the physical limits of competing SRAM and DRAM architectures, the shift toward heterogeneous data centers, and the strategic semiconductor competition between the US and China.
Why 100 Tokens Per Second Is the New Batch Mode
Cerebras CTO Sean Lie explains the roadmap to 10,000 tokens per second and why slow inference kills agentic reasoning.
Why Discrete SRAM Chips Hit a Wall on Frontier Models
Sean Lie explains why small SRAM chips like Groq struggle on trillion-parameter models and how wafer-scale chips solve the memory wall.
Why AI Data Centers Can't Remain Uniform GPU Clusters
Sean Lie explains why gigawatt data centers require disaggregated silicon and why models designed for Nvidia leave massive speed on the table.
OpenAI Jalapeño and Cerebras: Why AI-First Chip Design Wins
Sean Lie explains why OpenAI designed Jalapeño with AI tools, deployed Cerebras for live outages, and how prefill and decode split compute.
China Owns 95% of Open Source AI: Sean Lie on the Hardware Trap
Cerebras CTO Sean Lie explains why Chinese labs dominate open weights, how Huawei hardware fits in, and why Silicon Valley cannot win alone.