Arm CEO Rene Haas on AI Chip Design and the Path to GDS2

Key Takeaways

• Chip development cycles span 24 to 36 months, with the bulk of that time consumed by verification, validation, and documentation rather than initial logic design.
• Between 80 and 90 percent of Arm engineers now use AI tools on a daily basis to accelerate debugging and testing.
• Public models cannot generate complex silicon because proprietary hardware datasets remain locked inside private archives, giving incumbents with deep testbench logs a clear edge.
• Within five to ten years, Haas projects AI will produce fab-ready GDS2 files directly from concept prompts for simpler chip architectures.

The Real Bottleneck in Silicon Is Verification

Silicon engineering has a dirty secret: writing architecture is fast, but proving it works takes years. A typical chip takes between 24 and 36 months to produce. Most software founders assume that timeline exists because drawing logic gates is hard. It is not.

Arm CEO Rene Haas points out that the front-end architecture and register-transfer level (RTL) generation are rarely the problem. “The actual design of the architecture, the RTL generation if you will, the mapping of the architecture is not the largest amount of time,”▶ 8:06 Haas explained. “The largest amount of time is in the verification, the validation, the debug, the documentation. AI is really good at that.”▶ 0:19

Catching edge cases inside billions of transistors requires writing millions of automated test routines. When an engineer tweaks a memory bus, downstream subsystems break in subtle, intermittent ways. Human engineers spend months reading trace logs, writing coverage tests, and updating internal specs. Because these tasks resemble code review and text processing, language models excel at them. Inside Arm, AI adoption is no longer an internal pilot. Between 80 and 90 percent of their engineers use AI tools every day. Haas compares turning off AI access inside Arm to giving engineers internet access for only two hours a day in the 1990s.

Private Datasets Gate the Path to GDS2

Everyone wants a single prompt that outputs a production tape-out file. Haas believes that for simpler chips, moving directly from an idea to a GDS2 file (the final binary format sent to foundries like TSMC to print physical masks) is coming within five to ten years.

Getting there for complex silicon is harder because the training data does not exist on the open web. An LLM trained on public GitHub repositories cannot design high-end server silicon. Foundries and chip designers protect their physical layouts, timing closure scripts, and bug logs behind strict non-disclosure agreements. If the data is private, off-the-shelf models cannot learn it.

“It's unusable and it's untestable,”▶ 9:57 Haas noted regarding unstructured, unverified code bases. “And if it's unusable and untestable, it's actually untrainable. And if it's untrainable, it's not usable for AI.”▶ 9:59

This creates an advantage for incumbents. Arm has decades of validated IP, structured documentation, and test benches. Fine-tuning models on private verification archives turns internal repositories into compounding productivity loops that public model providers cannot match.

What to Do With This

Audit your engineering team's sprint logs from the past month to find where your developers spend more than 50 percent of their time on test writing, regression verification, or documentation. Point your internal AI tooling directly at those review queues rather than using it just for greenfield code drafting. If you maintain proprietary test datasets, structure them into fine-tuning pipelines this quarter before your competitors build similar data flywheels.