Key Takeaways

  • Big tech companies rely heavily on ASIC houses like Broadcom, a $2 trillion company, to handle the physical layout and packaging of custom chips.
  • Handing off front-end logic to a third party locks companies into standardized physical designs and slows their ability to adapt to new model architectures.
  • Fractile runs a full-stack silicon team of 150 people that covers everything from AI workload research to physical placement and advanced packaging.
  • Owning the entire pipeline from logic down to the final bitmap sent to TSMC allows startups to make sharp architectural bets, such as moving to high-bandwidth DRAM.

The Broadcom Trap for Custom Silicon

When a hyperscaler decides to build an AI chip, it rarely builds the entire chip in-house. The standard playbook is simple: internal software engineers write the high-level front-end logic that defines what the chip should do, and then they hand that blueprint over to an ASIC design firm.

As Walter Goodwin points out, “these are chips that are ultimately developed and delivered in partnership with kind of a relatively small number of what we might call ASIC houses, these kind of back-end delivery houses. Broadcom is the largest at, you know, $2 trillion company that help people kind of realize these designs.”

This division of labor looks efficient on a spreadsheet. It lets software companies avoid the massive overhead of building a physical chip implementation team. But Goodwin argues that this handoff creates a structural ceiling on performance. When you pass your logic over the wall, the ASIC house applies standard physical design templates, standard routing, and standard memory interfaces. The end result is predictable: every hyperscaler ends up with silicon that looks almost identical under the hood.

Why 150 Engineers Can Beat the Standard Playbook

Fractile took the opposite path. Instead of stopping at the architectural concept, the startup handles physical design, placement, and advanced packaging internally.

Goodwin explains why this integration matters: “inside Fractile we do have front-end designers, we have our own physical design team, we have our own kind of backend implementation team, we do our own work on advanced packaging for example, and that's not an enormous headcount. Fractile today is about 150 people.”

When front-end logic designers sit next to backend packaging engineers, the feedback loop changes completely. In a typical outsourced model, translating architectural intent into the bitmap that gets manufactured at TSMC is a one-way street. If a physical routing bottleneck appears late in the cycle, the external design house works around it with generic fixes rather than rethinking the underlying architecture.

Goodwin notes that in the traditional process, “that kind of front-end design that describes the kind of underlying intent of the chip, the underlying logic of the chip is then transformed ultimately into something that you know what gets shipped to TSMC in the end is literally a kind of bitmap.” When you outsource that transformation, “you get to a certain level and then you hand off to another partner and at some to some extent you're kind of at the mercy of how that other partner then behaves.”

Owning the entire stack gave Fractile the speed needed to pivot its memory architecture away from on-chip SRAM toward high-bandwidth DRAM as frontier inference workloads shifted. A company stuck in an outsourced ASIC delivery pipeline would have spent quarters renegotiating specifications with an external partner.

What to Do With This

Audit your core product architecture to identify where you hand off critical execution to third-party vendors. If your primary competitive advantage depends on the speed of that feedback loop, hire the specialized talent to bring that step in-house this quarter, even if it requires building a dedicated 5-person physical or systems engineering pod.