Intel on Ruthenium and CFET: Why Copper Fails at 20 Nanometers
Intel researcher Jack Kavalieros explains why copper interconnects fail below 20nm and how CFET vertical stacking de-risks future chips.
What will computer chips look like in 2045?
With Dwarkesh Patel, Chris Auth, Kevin Fischer, Jack Kavalieros, Tyler Osborn, Pushkar Ranade · Sunday, October 25, 2026
Dwarkesh Patel tours Intel's advanced manufacturing facilities and research labs to investigate the future of semiconductor hardware through 2045. Intel technical leaders detail the development of gate-all-around transistors, backside power, CFET architectures, and hybrid bonding, while Chief Technology Officer Pushkar Ranade addresses the severe equipment supply bottlenecks constraining global chip production amid soaring AI compute demand.
Key takeaways
- Copper interconnects lose electrical performance at a 20-nanometer pitch because the mandatory barrier liner consumes too much cross-sectional area. Read more →
- Monolithic dies hit an area-versus-perimeter bandwidth wall, pushing advanced chip design from planar 2.5D interposers into direct 3D hybrid bonding. Read more →
- Intel set overambitious density targets on its 10-nanometer node through hyperscaling, trying to shrink transistor dimensions without waiting for ready extreme ultraviolet (EUV) lithography tools. Read more →
- Leading-edge chip manufacturing requires making major production calls on incomplete data; waiting for full certainty guarantees missing customer delivery windows. Read more →
- ASML produces fewer than 100 extreme ultraviolet (EUV) lithography tools per year and will not expand far beyond that mark by 2030. Read more →
5 articles from this episode
Tyler Osborn on Hybrid Bonding: Why Logic Packaging Is Going 3D
Tyler Osborn explains how sub-micron hybrid bonding eliminates interconnect layers, cuts picojoules per bit, and changes chip architecture.
Intel 10nm Delay: Limit Inventions to Hit Node Deadlines
Intel delayed its 10nm node by stacking unready tools. Chris Auth explains how the phase gate method caps unproven tech to keep manufacturing on schedule.
Kevin Fischer on Intel Yield: Stop Waiting for Complete Data
Kevin Fischer explains why Intel uses HotBox 1 scheduling to clear factory tools and fix yield-killing wafer defects with incomplete data.
ASML Tools Cap AI Chip Scaling at 2x
Intel CTO Pushkar Ranade explains why $400M tool limits and ASML shortages cap global chip scaling at 2x despite surging AI compute demand.
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