Key Takeaways

  • ASML produces fewer than 100 extreme ultraviolet (EUV) lithography tools per year and will not expand far beyond that mark by 2030.
  • While AI compute demand grows 3x each year, global leading-edge wafer output can grow only about 2x in total, even with unlimited capital expenditure.
  • Advanced fabs run on an 80% fixed-cost structure, meaning minor drops in factory capacity destroy profit margins.
  • Advanced process flows like Intel 18A lock into specific tool vendors; switching to alternative machinery requires qualifying an entirely new manufacturing line.
  • A single High-NA EUV scanner costs $400 million today, threatening to double patterning costs over the next four years.

Capital Cannot Buy Tools That Do Not Exist

Software founders assume compute scales like cloud instances: if you write a check, the servers appear. Silicon manufacturing does not care about your checkbook. AI compute appetite is climbing by roughly 3x every year, but the physical equipment required to print top-tier silicon is hitting a wall.

The central bottleneck is ASML in the Netherlands. As Dwarkesh Patel pointed out during his tour of Intel's research facilities, “For this EUV tool, ASML produces fewer than 100 of them a year.” ASML has no plans to expand that output even by the end of the decade.

That is not a temporary supply chain blip. It is a physical limit. Building an EUV scanner requires thousands of specialized optics, laser sources, and sub-assemblies from hundreds of vendors. Pushkar Ranade, Intel's Chief Technology Officer, made the reality blunt: “Unless the entire supply chain, starting from the equipment suppliers, their suppliers, their sub-suppliers, unless everybody produces more, you can’t increase the output.”

Even if hyperscalers pour unlimited money into fabs, total global output of leading-edge wafers will grow only roughly 2x over this cycle. The chips cannot be stamped out faster.

The 80% Fixed-Cost Trap

When foundries face tool constraints, they cannot swap machines like software engineers swap cloud regions. Once an architecture locks into place, changing hardware suppliers is off the table.

Ranade explained the trap: “Even though there are multiple providers of other tools, once you lock into a process flow, let’s say 18A, which is a mature process now, we need a specific tool. We can’t just go and get a different tool for the same process.”

That rigidity collides with brutal factory economics. Building an advanced fab costs tens of billions of dollars, and tool lead times stretch past 18 months. “Once you build a fab, like 80% of your cost structure is fixed,” Ranade noted. With fixed overhead running that high, every single percentage point of factory throughput directly dictates whether a fab survives financially.

Because 80% of the cost is sunk on day one, foundries must run at maximum volume on existing machines. They cannot pause production to test unvetted tools. Meanwhile, equipment prices are exploding. As Ranade pointed out, “Today, a High-NA EUV scanner and all its associated equipment costs like $400 million. So what does that mean? If that rate were to continue, if you just draw the line, does that mean four years from now the cost of patterning is going to be like $800 million?”

When each machine costs half a billion dollars and process recipes cannot change, hyperscalers end up bidding against each other for fixed foundry lines.

What to Do With This

Audit your compute budget for the next 24 months tomorrow morning. If your unit economics rely on leading-edge inference becoming 5x cheaper purely from chip hardware improvements, rewrite your model to assume flat pricing. Sign multi-quarter reservations with your cloud provider now for specific GPU tiers, and shift engineering sprints toward model distillation and quantization rather than waiting for next-generation hardware to rescue your margins.