Key Takeaways

  • Copper interconnects lose electrical performance at a 20-nanometer pitch because the mandatory barrier liner consumes too much cross-sectional area.
  • Intel plans to replace copper with ruthenium below 20 nanometers because ruthenium can be etched directly without an insulating liner.
  • Complementary field-effect transistors (CFET) stack NMOS directly on top of PMOS, relaxing lateral density pressure through 2045.
  • Research director Jack Kavalieros isolates extreme vertical aspect-ratio risks by testing simplified single-wire CFET vehicles before building multi-layer production chips.

Copper Fails When the Liner Steals the Wire

When chip features shrink toward single-digit nanometers, interconnect wires carry signals across billions of transistors. For decades, copper reigned as the conductor of choice. But copper has a fatal flaw at atomic dimensions: copper atoms migrate into surrounding silicon oxide layers, causing short circuits. To prevent drift, chipmakers line every copper trench with a protective barrier layer.

At 100-nanometer pitches, that barrier liner takes up a negligible sliver of space. At a 20-nanometer pitch, the liner stays thick while the copper core shrinks to a thread. The resistive liner consumes the volume where current needs to flow. Electrical resistance spikes, and clock signals slow down.

Jack Kavalieros, who directs transistor research at Intel, points out that the material physics must change once dimensions cross that line.

“There is a crossover point where ruthenium will have much better conductivity, better resistivity than copper. That’s roughly in the 20-nanometer pitch range,” Kavalieros says.

Ruthenium solves the liner problem because it behaves differently during manufacturing. Copper cannot be etched cleanly with standard reactive chemicals; chipmakers must carve trenches in an insulator, line them, fill them with copper, and polish away the excess. Ruthenium bypasses that constraint.

“Ruthenium is very different in that regard because it’s a material that we can actually etch,” Kavalieros explains. “As such, by etching it, we don’t need that liner. Now you scale those very fine dimensions, and if you can trade off that resistive liner with no liner, ruthenium starts to win.”

Stacking Transistors Without Full-Stack Complexity

Shrinking transistors laterally is running out of physical room. The next structural transition is the complementary field-effect transistor, or CFET. Instead of printing NMOS and PMOS transistors side by side on a flat silicon wafer, CFET places one directly above the other.

“We’re taking transistors that had to be compressed more and more, and we’re relaxing that in some ways because we’re going to stack them on top of each other,” Kavalieros notes. “But the act of stacking does not mean that they’re not interconnected.”

Stacking doubles transistor density per unit area, but creates severe processing challenges. Etching deep, narrow vertical trenches requires aspect ratios that push plasma chemistry to its limit. If you deposit metal into a trench that is twenty times deeper than it is wide, voids form inside the contact.

Intel avoids spending months building full production-grade stacks to test basic feasibility. Instead, Kavalieros relies on isolated short-loop test vehicles.

“Our goal here is to take unit cells of that process and qualify them,” Kavalieros says. “We take advantage of short-loop vehicles that can give us electrical parameters, chemical parameters that can resolve some of those challenges, those speed bumps.”

Rather than building a complete logic gate with full routing, Intel fabricates bare-bones hardware cells designed to isolate one variable.

“So we would have a simplified version of a CFET, which has only one wire for the NMOS and one wire for the PMOS,” Kavalieros explains. “That simplifies our job, but it still helps us evaluate the stacking of devices and how they will interconnect.”

What to Do With This

Audit your core product development cycle tomorrow. Find the subsystem where multiple unproven components are being tested inside a single end-to-end prototype, strip away the non-essential interfaces, and build a single-variable test harness that returns electrical, chemical, or operational metrics within 48 hours.